1. Technical Field of the Invention
This invention is related to methods, devices, and systems for configuring I/O devices. More particularly, this invention relates to the delegation and control of one or more functions in a multi-function device adapter. The present invention even more particularly relates to configuring multi-function I/O device adapters to facilitate functional control and delegation of one or more functions of a multifunction device adapter by a device located at another function slot within the multifunction adapter.
2. Description of Related Art
The peripheral component interconnect ("PCI") local bus is an industry standard I/O bus that interconnects computer processor complexes to I/O device adapters. The computer processor complex typically contains a central processing unit (CPU) and system main storage facility. A PCI I/O device adapter contains hardware, and possibly additional processors and programming to interconnect I/O devices such as disks, computer network interfaces, and other peripherals to the processor complex and to control the functions of these I/O devices.
The PCI local bus specification was developed and is controlled by a special interest group formed of a variety of I/O device and computer system vendors that are influential within the personal computer and PC server industry. This specification is defined expressly as a higher performance replacement for other existing I/O bus architectures such as the IBM microchannel and extended industry standard architecture ("EISA").
As such, the PCI local bus specification represents the dominant I/O bus architecture within a very large segment of the computer industry. Furthermore, the PCI local bus specification has been embraced outside of this segment by vendors that participate primarily in other markets, such as enterprise-class network server and mainframe computers. Thus, the scope of computer system and I/O device products that employ PCI local bus implementations is rapidly becoming the majority within the overall computer industry.
In the PCI Local Bus Specification, the physical/electrical connections to the PCI bus and PCI bus signaling protocols specify the addressing of a particular PCI bus connection, or "agent slot," using the PCI Local Bus "Configuration Read" or "Configuration Write" signaling protocols. This is accomplished through use of a "device number", which serves to identify a particular connection or agent slot. This configuration protocol allows the Processor Complex to individually address each PCI Local Bus connection using a physical selection signal that is part of the PCI bus signal definitions, and to assign to each I/O Device Adapter a range of Processor Memory addresses by which the processor may subsequently communicate with the corresponding I/O device adapter.
FIG. 1 illustrates the basic elements of a common PCI Local bus implementation, comprised of a Processor Complex 100 connected to a PCI backplane 200 which in turn is connected to one or more I/O devices 280. The processor complex 100 includes a central processing unit ("CPU") 110 and a memory 120 interconnected via a processor bus 130.
In a conventional PCI local bus implementation, the PCI backplane 200 is normally provided on the motherboard with a PCI local bus 230. The PCI local bus 230 is typically connected to the processor memory bus 130 by a PCI host bridge 210. One or more PCI connectors 205 then connect one or more removable PCI multi-function devices 260 to the PCI local bus 230. While FIG. 1 illustrates only a single removable PCI multi-function device 260, as already explained, the PCI local bus specification supports multiple bus connections or "agent slots". Thus, multiple multifunction devices 260 may be connected to the PCI local bus 230. Although the present application is primarily directed to operation of removable PCI multi-function devices 260, the PCI specification also supports PCI devices, and both single and multi-function devices need not be removable.
As already explained, a PCI host bridge 210 interconnects the PCI local bus 230 to the processor memory bus 130 over which the CPU 110 and memory 120 communicate. The PCI host bridge 210 supplies information between the PCI local bus 230 and the processor memory bus 130, converting information from the processor complex 100 to the PCI bus specification, and converting information obtained from the PCI local bus 230 from the PCI local bus specification to an information format readable by the processor complex 100. A PCI multi-function device 260, as illustrated in FIG. 1, allows multiple functions to be accessed with a single PCI "device number" at a single PCI bus connection or agent slot.
The removable PCI multi-function device 260 includes a function router 270 for routing data and/or control signals between the processor complex 100 and a selected function of the removable PCI multi-function device. An I/O device adapter 252,254 controls each function of the removable PCI multi-function device 260. Each I/O device adapter can connect to a single or multiple I/O devices 280. Typically, the function router 270 includes a multiplexer to route the data and/or control signals between the processor complex 100 and a selected one of the multiple I/O device adapters 252,254.
In such a conventional system, a PCI multifunction device 260 collects multiple PCI I/O device adapter functions to a single PCI local bus connection or agent slot. This allows increasingly dense physical integration and increased functionality as components shrink in size and increase in power. Further, multiple functions with a single removable PCI multi-function device 260 enables an increased number of I/O device adapters without adding more agent slots on the PCI local bus 230 or its associated PCI back plane 200.
In FIG. 1, the I/O device adapters 252,254 have been integrated into a single PCI multi-function device 260 through the use of the function router 270. To enable the processor complex 100 to select a particular I/O device adapter, or "function" resident at this specific PCI bus connection or "agent slot", the PCI local bus specification configuration protocol appends to the device number a function number having 3 bits, thus accommodating functions 0 to 7. In this fashion, a single PCI multi-function device 260 may accommodate up to 8 single function devices through the use of this extended definition. Thus, the processor complex 100 may specify any of the function numbers 0 to 7 controlled by the PCI multi-function device 260, in essence allowing each PCI bus connection or "agent slot" to accommodate up to 8 I/O device adapters.
Under this system, single function devices are accommodated by this extended definition by assigning single function devices with a 3 bit code indicative of "function 0". In essence this treats a single function PCI device as a simplified case of a multi-function device whose function router component only implements one function: function 0.
The PCI multi-function device 260 is accordingly architecturally capable of incorporating up to 8 I/O device adapter elements within a single device, requiring a single PCI agent slot on the PCI local bus. It is accordingly apparent that the function router 270 of FIG. 1 must facilitate the sharing of the single PCI agent slot among multiple I/O device adapter functions incorporated within the multi-function device. In particular, during configuration read and write protocols, the function router 270 uses the function number from this protocol to route the arguments of this protocol between the PCI local bus and the assigned PCI I/O device adapter 252,254 and associated I/O device 280.
One limitation of the PCI local bus specification is the lack of any provision for the determination of which functions of a multi-function device must be presented directly to the host (normally the processor complex) through the PCI local bus function configuration space. Within a multi-function device, it is desirable to allow an I/O device adapter at one function space of the multi-function device to perform complete access and control of an I/O device adapter present at another function space based on the overall configuration of the I/O device adapters attached to the multi-function device.
An example of this type of configuration activity is that of a controller which will perform host or processor complex interface activity on behalf of one or more generic I/O device adapters attached to separate function locations of the multi-function device. In this circumstance, the PCI bus specification does not have any system for allowing one function of the multi-function device to be controlled or accessed by another function within the multi-function device. Thus, under the current PCI bus specification, each function of the multi-function device must be accessed and controlled by the processor complex as local control of one function by an I/O device adapter at another function space within the multi-function device is not contemplated by the current PCI bus specification.